Due to the high integration density of modern electronic circuits and storages, the frequency of errors increases.
Therefore, the implementation of error detection mechanisms in such electronic circuits is of high interest. One possible implementation of such error detection mechanisms is the design of self-checking structures within electronic circuits, i.e. structures which detect their own faults during normal operation. Since comparators are often used for the design of self-checking circuits it is of special interest to design simple comparators which detect their own internal faults during normal operation.
FIG. 8 illustrates a conventional comparator. By the comparator of FIG. 8, the data words u=u1, . . . , un and u′=u′1, . . . , un′ are compared with respect to uniformity or equality. If u and u′ are not equal, an error signal y=1 is output at the output 16 of the comparator. If u and u′ are equal, a signal y=0 is output at the output 16 of the allocator 15.
The comparator consists of XOR operator VXOR 17 having 2n=8 inputs to which the components u1, u2, u3, u4 and u1′, u2′, u3′, u4′ of the data words u and u′ are applied and n outputs for outputting an n digit XOR combined value v=v1, . . . , vn. In FIG. 8, n=4 was selected. Connected downstream from the XOR operator VXOR 17, an OR gate 15 having n=4 inputs is connected for inputting the XOR values v1, . . . , vn and having an output for outputting an error signal y.
The XOR values v=v1, . . . , v4 are formed according to the following relationsv1=u1⊕u1′v2=u2⊕u2′v3=u3⊕u3′vn=un⊕u4′from which then the output value y of the comparator is determined
  y  =                    ⩔                  i          =          1                    4        ⁢                  v        i            .      
The XOR operator 17 of FIG. 8 consists of the 4 XOR gates 11, 12, 13 and 14, each comprising two inputs and one output.
First, the recognizability of errors of the comparator in running operation is considered.
At the XOR gate 11, at its two inputs the values u1, u1′ are applied which are equal as long as no error occurs in u or u′. At the XOR gate 11, thus only the values 0, 0 or 1, 1 are applied, which are each combined to 0 and are output at its output and thus at the first output of the XOR operator 17 carrying the signal v1. Similarly, at the further XOR gates 12, 13 and 14 of the XOR operator VXOR 17, as long as no error occurs in u or u′, only the values 0, 0 or 1, 1 are applied and at their outputs the value 0 is output. At the n=4-component output of the XOR operator, thus always the value v=v1, v2, v3, v4=0, 0, 0, 0 is output, as long as u and u′ are not different.